1. Field of the Invention
The present disclosure is generally related to data processing, or, more specifically, methods, apparatus, and products for semiconductor layout generation.
2. Description of Related Art
Semiconductor circuits are generally brought into existence in two phases. In a first phase the circuit is designed. In a second phase, the circuit is fabricated on a semiconductor die. During the design phase, a circuit designer may create a layout of a circuit on a computer storage device to be used during the fabrication phase to fabricate the circuit on the silicon wafer.
Current methods to ensure that such layout can be fabricated without failure are often inefficient and sub-optimal. For example, the fabrication process may be changed after the circuit design and layout are complete but before fabrication. Thus, the layout, if fabricated as originally designed, would result in sub-optimal yield in semiconductor manufacturing. Also, a layout may be compliant to an individual design rule, but may not yield when multiple fail modes interact with each other. Further, density critical layouts are usually designed sub-ground rules. However, there is no automated way to guide design to minimize overall process fails.